The present disclosure relates to a Galois field arithmetic operation circuit being used as an error detection & correction circuit, and a memory device.
A NAND flash memory is known as one type of electrically erasable and programmable read only memory (EEPROM). A NAND flash memory uses a NAND cell unit (a NAND string) for which a plurality of memory cells are serially connected to one another. A NAND flash memory can store a large amount of data in a small area.
In a NAND flash memory, data content may be damaged due to various causes while keeping the data. For example, due to deterioration of a tunnel oxide film caused by performing a rewrite operation several times, a characteristic of memory device (memory cell) is deteriorated while keeping data and thereby an occurrence ratio of error bits (an error ratio) tends to increase. In particular, in a NAND flash memory, an error ratio tends to increase while a large-scale increase of memory capacity and miniaturization of manufacturing process are proceeding. To cope with that, an error detection & correction circuit is used to improve performance of a NAND flash memory. By mounting an error detection & correction circuit in an on-chip form, a high reliability memory can be provided.
Japanese Patent No. 06-314979, which is incorporated by reference herein in its entirety, describes a Galois field multiplier circuit that uses a Galois field arithmetic operation circuit by finite field (Galois field) (GF(2^m)). The Galois field arithmetic operation circuit, when doing multiplication of two elements vector-expressed by m-bits on the Galois field (GF(2^m)), operates an exclusive OR (EXOR) with respect to components of high-order bits except a low-order m-th bit during the multiplication operation and obtains a multiplied vector output by converting the operational output into a vector expression of m bits by a given primitive polynomial (f(X)), and then performing an exclusive OR (EXOR) on the vector expression and a component of a low-order m-th bit. Accordingly, a Galois field arithmetic operation circuit attempts simplification of a multiplication circuit constitution.